UT54LVDS217 LVDS Serializer

Estimated 8 week lead time for prototypes; 10 week for HiRel, 18 weeks for QML Q, 20 weeks for QML V

Log in for pricing

The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel and data throughput is 1.575 Gbit/s (197 Mbytes/sec).

The UT54LVDS217 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size.
All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.



  • General LVDS serial data link (x3) + clock transmission (x1) at high aggregate data rates
  • General systems requiring aggregate data rates up to 1.575 Gbps (bits) or 197 MBps (bytes)


  • 15 to 75 MHz shift clock support
  • Low power consumption
  • Power-down mode <216µW (max)
  • Cold sparing all pins
  • Narrow bus reduces cable size and cost
  • Up to 1.575 Gbps throughput
  • Up to 197 Megabytes/sec bandwidth
  • 325 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Rising edge strobe
  • Operational Environment; total dose irradiation testing to MILSTD-883 Method 1019
    • Total-dose: 300 krad(Si) and 1 Mrad(Si)
    • Latchup immune (LET > 100 MeV-cm2/mg)
  • Packaging options:
    • 48-lead flatpack (1.4 grams)
  • Standard Microcircuit Drawing 5962-01534
    • QML Q and V compliant part
  • Compatible with ANSI/TIA/EIA-644 Standard

Log in for pricing