UT200SpWPHY01 SpaceWire Physical Layer Transceiver


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Minimum Purchase:
5 units
Maximum Purchase:
250 units

The UT200SpWPHY01 Physical Layer Transceiver (PHY) is designed to handle the critical timing issues associated with the SpaceWire Data/Strobe Encoding scheme.  The receiver operates on both edges of the recovered RxClk and provides data on the digital outputs in bit pairs. The transmitter operation is the reverse of the receiver. Bit pairs of data and strobe are written into the device on the WrClk signal and the PHY serializes data and strobe onto the LVDS bus using the TxClk signal. The advantages of this SerDes functionality is the interfacing FPGA or ASIC can run at reduced clock rate with high-speed clock not requiring a stringent phase relationship.



  • 2-bit Serializer/Deserializer (SerDes) functionality
  • LVDS physical layer
  • Data rates to 200 Mbits/sec
  • Data/Strobe transmit skew <500pS
  • 3V power supply
  • Cold spare on LVDS pins
  • Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 100 krad(Si) - Latchup immune (LET > 109 MeV-cm2/mg)
  • ESD rating Class 1
  • Packaged in a 28-pin flatpack
  • Standard Microcircuit Drawing 5962-06232 - QML Q and V compliant part
ECCN Number:

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