UT32BS1X833 Matrix-D™ 32-Channel 1:8 Bus Switch


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The UT32BS1X833 Matrix-D™ is a 32-Channel, 1:8 Bus Switch, that provides bus isolation for up to eight banks of 32 I/O connections. By providing bus isolation, the UT32BS1X833 can significantly reduce the amount of load capacitance seen by a host processor and memory devices. The enable to output delay time is only 4.1ns (typical). The reduction in both load capacitance and delay time significantly increase speed and performance compared with a discrete logic or FPGA memory interface solution.  The UT32BS1X833 operates from a single 3.3V supply. The bus channels can pass any voltage between VSS and VDD, allowing the switching of signals using other standards, such as LVCMOS 1.8V.  The input and output banks connect via analog channels that have an RON that is nominally 5 Ohms over the entire input voltage range. The flat RON eliminates the need to add external series resistors for source impedance termination.  The UT32BS1X833 has a “broadcast mode” that is enabled by driving both SDCS[1] and SDCS[0] low. In this mode, all banks are active, which facilitates SDRAM refresh and initialization cycles.  Each UT32BS1X833 can interface up to eight of the Cobham
2.5Gb or 3.0Gb SDRAM MCM devices with any Cobham LEON processor without the need for additional logic.


 Interfaces to standard processor memory busses
 Single-chip interface that provides memory paging to industrystandard SDRAMS
 Eliminates need for additional logic or FPGA
 I/O channels functional to 3.3V
 RON 5 Ohms typical
 Flat RON characteristics over channel voltage
 Propagation delay 204ps through switch
 Transmission gate technology allows for true bi-directional operation
 Internal pull-up resistors on the first 8 outputs of each bank to ensure memory devices remain in off state when channels deselected
 Bus holders maintain output states on all other outputs when channels de-selected
 Logic power 1mW/MHz
 Temperature range -55°C to 125°C
 Operational environment:
- Intrinsic total-dose: up to 300 krad(Si)
- SEL Immune <100 MeV-cm2/mg
 Packaging options:
- 400-pin Ceramic Land Grid, Column Grid and Ball Grid
Array packages; 1mm pitch
 Standard Microcircuit Drawing 5962-15243
- QML Q and V


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