UT32M0R500 Arm® Cortex®-M0+ 32-bit Microcontroller

Estimated lead times: Prototypes 8 weeks, Hi Rel 10 weeks; Lean Rel 14 weeks. For ceramic ball grid array (CBGA), add 8 weeks. For ceramic column grid array (CCGA), add 24 weeks.

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The UT32M0R500 microcontroller utilizes the Arm® Cortex®-M0+ 32-bit processor with a RISC based architecture operating at a 50 MHz frequency. The microcontroller includes a memory protection unit (MPU), embedded memories, with several peripherals including support for CAN 2.0B. For increased design flexibility, the microcontroller includes several analog features such as an analog signal channel with a multiplexed input combined with a programmable gain amplifier and analog-to-digital converter, two digital-to-analog converters, two analog comparators, and precision current source.

The UT32M0R500 incorporates a variety of power-saving modes to facilitate the design of low-power applications. The UT32M0R500 is supported by the Keil® Development Tool Environment.

For information on the Arm® Cortex®-M0+ core please refer to the Arm® Cortex®-M0+ Technical Reference Manual, available from the www.arm.com website.



  • Space VPX Chassis Management
  • CAN Bus Controller
  • Telemetry/System Health Monitoring
  • Distributed Command and Control
  • Data Acquisition Manager
  • FPGA Scrubber
  • FPGA + PMBus Power Management
  • RF Signal Chain Management


  • Single 3.3 V Supply Voltage (3.0 V to 3.6 V)
  • System
    • Arm® Cortex® M0+
    • Arm® Cortex® M0+ built-in NVIC
  • Digital and Communication Peripherals
    • 2x CAN 2.0B Controllers
    • 2x UART
    • SPI
    • 2x I2C
    • JTAG
    • 4x General purpose timers
    • 3x PWM
    • Watchdog Timer
    • Real Time Clock
    • 48x GPIO (21 dedicated)
    • 8x Hardware Interrupts (shared with GPIO)
  • Analog Peripherals
    • 12-bit ADC 100 ksps with PGA
    • 16 Single Ended or 8 Differential Channels
    • 1 mA Precision Current Source
    • 2x 12-bit DACs
    • 2x Analog Voltage Comparators
    • Temperature Sensor
  • Power Control
    • Multiple power modes for low power optimization
    • System clock scalable for low power
  • Memories
    • 96KB Dual Port SRAM with EDAC + Scrubbing
    • 64Mb Flash Memory
    • 384KB in 96KB increments for user firmware
  • Clock Generation
    • 50 MHz internal clock factory-trimmed RC
    • Support for external clock source and crystal oscillator
  • Standard Microelectronics Drawing (SMD):
    • 5962-17212 (QML Q and Q+)
  • Package Options:
    • 143-Pin
      • Ceramic Land Grid Array
      • Ceramic Column Grid Array
      • Ceramic Ball Grid Array (Prototype Only)
    • 14.5 x 14.5 mm, 1 mm pitch

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