UT54ACTS169 MSI Logic TTL Inputs


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ð  Fully synchronous operation for counting and programming

ð  Internal look-ahead for fast counting

ð  Carry output for n-bit cascading

ð  Fully independent clock circuit

ð  1.2μ CMOS

- Latchup immune

ð  High speed

ð  Low power consumption

ð  Single 5 volt supply

ð  Available QML Q or V processes

ð  Flexible package

- 16-pin DIP

- 16-lead flatpack

ð  UT54ACS169 - SMD 5962-96560

ð  UT54ACTS169 - SMD 5962-96561





The UT54ACS169 and the UT54ACTS169 are synchronous 4- bit binary counters that feature an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable inputs and internal gating. Synchronous operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters. The clock input triggers the four flip-flops on the rising (positive-going) edge of the clock.


The counters are fully programmable (i.e., the outputs may each be preset high or low). The load input circuitry allows loading with the carry-enable output of cascaded counters. Loading is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.


The carry look-ahead circuitry provides for cascaded counters for n-bit synchronous application without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output. Assert both count enable inputs (ENP and ENT) to count. The direction of the count is determined by the level of the U/D input. When U/D is high, the counter counts up; when low, it counts down. Input ENT is fed forward to enable the carry output. The ripple carry output RCO enables a low-level pulse while the count is zero (all inputs low) counting down or maximum (15) counting up. The low level overflow carry pulse can be used to enable successive cascaded stages.


Transitions at ENP or ENT are allowed regardless of the level of the clock input. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, U/D) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The devices are characterized over full military temperature range of -55ðC to +125ðC.


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