UT54ACTS190 MSI Logic TTL Inputs


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ð  Single down/up count control line

ð  Look-ahead circuitry enhances speed of cascaded counters

ð  Fully synchronous in count modes

ð  Asynchronously presettable with load control

ð  1.2μ CMOS

- Latchup immune

ð  High speed

ð  Low power consumption

ð  Single 5 volt supply

ð  Available QML Q or V processes

ð  Flexible package

- 16-pin DIP

- 16-lead flatpack

ð  UT54ACS190 - SMD 5962-96562

ð  UT54ACTS190 - SMD 5962-96563





The UT54ACS190 and the UT54ACTS190 are synchronous 4- bit reversible up-down BCD decade counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed. Synchronous operation eliminates the output counting spikes associated with asynchronous counters.


The outputs of the four flip-flops are triggered on a low-to-high level transition of the clock input if the enable input (CTEN) is low. A logic one applied to CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down.


The counters feature a fully independent clock circuit. Changes at control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs.


The counters are fully programmable. The outputs may be preset to either logic level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. The asynchronous load allows counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.


If preset to an illegal state, the counter returns to a normal sequence in one or two counts.


Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum (MAX/MIN) count. The MAX/MIN output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (9) counting up. The ripple clock output (RCO) produces a low-level output pulse under those same conditions but only while the clock input is low. The counters easily cascade by feeding the RCO to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. Use the MAX/MIN count output to accomplish look-ahead for high speed operation.


The devices are characterized over full military temperature range of -55ðC to +125ðC.


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