UT64BS1X433 Matrix-A Bus Switch


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The UT64BS1X433 Matrix-A™ is a 64-Channel, 1:4 Bus Switch, that provides bus isolation for up to four banks of 64 I/O connections. By providing bus isolation, the UT64BS1X433 can significantly reduce the amount of load capacitance seen by a host processor and memory devices. The reduction in both load capacitance and delay time significantly increase speed and performance compared with a discrete logic or FPGA memory interface solution.  The UT64BS1X433 operates from a single 3.3V supply. The bus channels can pass any voltage between VSS and VDD, allowing the switching of signals using other standards, such as LVCMOS 1.8V.  The UT64BS1X433 has two modes of operation. In mode 0, the device uses five address and one chip select line to electrically connect the input bank to one of four output banks and generate 1 of 32 chip select outputs. In mode 1, the device uses eight address and two chip select lines to independently control two pairs of two banks with each bank pair controlled by one of the two chip selects.  Mode 1 allows the device to interface two different types of memory having different address bus configurations e.g. two PROM banks and two SRAM banks. The input and output banks connect via analog channels that have an RON that is nominally 5 Ohms over the entire input voltage range. The flat RON eliminates the need to add external series resistors for source impedance termination.  The UT64BS1X433 also provides logic to control up to eight discrete devices per bank by providing eight individual chip selects that are decoded using address lines ASEL[2:0] and BSEL[2:0].
In a fully utilized configuration, the UT64BS1X433 can select up to 32 discrete devices and provide bus isolation to each bank of eight devices. This makes the device ideally suited for use with mutli-chip module memory devices, such as the Aeroflex UT8R1/2/4M39 40/80/160Mbit family of SRAM devices. Each UT64BS1X433 can interface up to four of the Aeroflex 160Mb SRAM MCM devices with any Cobham LEON processor without the need for additional logic.


 Interfaces to standard processor memory busses
 Single-chip interface to industry-standard asynchronous SRAM and PROM memory devices
 Eliminates need for additional logic or FPGA
 I/O channels functional to 3.3V
 RON 5 Ohms typical
 Flat RON characteristics over channel voltage
 Propagation delay 204ps through switch
 Transmission gate technology allows for true bi-directional operation
 Bus holders maintain output states on all 64 channels when deselected
 Logic power 1mW/MHz
 Independent 5-bit address decoding to select 1 of 32 devices
 Temperature range -55°C to 125°C
 Operational environment:
- Intrinsic total-dose: up to 300 krad(Si)
- SEL Immune: <100 MeV-cm2/mg @ 125°C
 Packaging options:
- 400-pin Ceramic Land Grid, Column Grid and Ball Grid Array packages; 1mm pitch
 Standard Microcircuit Drawing 5962-15242 - QML Q and V

- Microprocessor interfaces that require large amounts of memory
- High-speed applications or systems with large bus capacitance
- Cost-sensitive app


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