UT7R2XLR816 Clock Network Manager


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The UT7R2XLR816 is a low voltage, low power, clock network manager. The device features 16-outputs in 8 banks of 2.  Independent power supplies for each bank (+2.25V to +3.6V) give the user great flexibility in multi- voltage systems. Outputs can be configured as LVCMOS (2.5V/8mA or 3.3V/12mA) or standard LVDS pairs. Independent output bank division and phase skewing empower the system designer to optimize output phase and frequency relationships throughout a clock network.  The skew controls enable outputs to lead or lag the reference clock while the ternary output divider control can divide the PLL oscillator frequency by any integer from 1to 32 before driving the clock out of the desired bank. Regardless of output divider settings, input and output clock edges are synchronized at start-up and whenever the device is removed from power down mode. Power down mode is controlled by the RST/DIV ternany input which also controls input division of the reference clock. Time units for skew control (tU) are 22.5o of the clock cycle for low and mid frequency oscillators and 45o of the clock cycle for the high frequency oscillator.



- +3.3V Core Power Supply
- Independent power supply for each clock bank
- Power supply range from +2.25V to +3.6V
- 8 Output clock banks with flexible I/O signaling
   - Up to 16 LVCMOS3.3 outputs with 12mA slew-rate limited, break-before-make, buffers, or
   - Up to 16 LVCMOS2.5 outputs with 8mA slew-rate limited, break-before-make, buffers, or
   - Up to 8 standard drive LVDS outputs
- Input clock multiplication of any integer from 1 - 32- PLL Operation
- Low frequency range: 24MHz to 50MHz
- Mid frequency range: 48MHz to 100MHz
- High frequency range: 96MHz to 200MHz
 Input reference clock signaling and control:
- LVCMOS3.3/LVTTL (Cold-Spared),
LVDS (Cold-Spared), &
Parallel Resonant Quartz Crystal
- Reference input divide-by-1 or divide-by-2
- Input frequency range from 2MHz to 200MHz
 Dedicated feedback Input/Output module
- Independent feedback power supply (+3.0V to +3.6V)
- 1-to-32 divider options with/without inverting
- Phase control -6, -4, -3, -2, -1, 0, 1, 2, 3, 4, 6 tU
- FB_IN: Not affected by RST/DIV state
- No Synchronous Output Enable (sOE) control in order to maintain PLL lock
 Output clock bank signaling and control:
- Output frequency range from 750KHz to 200MHz
- 1-to-32 divider options with/without inverting
- Odd bank phase control -4, -3, -2, -1, 0, 1, 2, 3, 4 tU
- Even bank phase control -6, -4, -2, -1, 0, 1, 2, 4, 6 tU
- Disable HIGH, LOW, or HIGH-Z (See Table 1, page 6)
- Synchronous Output Enable (sOE) control
- Outputs (0-7)Q0, 1 = HIGH-Z/Tri-state when RST/DIV= LOW (RESET)
- Guaranteed reference input to output edge synchronization
- Low inherent output bank skew (e.g. SKEW = 0*tU)
- < 50ps intrabank skew (typical)
- < 100ps interbank skew without dividing or inverting (typ)
- < 250ps interbank skew across divided or inverted banks (typ)
- Power dissipation can be reduced by powering down unused output banks (See Note 2, page 37)
Temperature range:
- HiRel: -55oC to +125oC

Operational environment:
- Total-dose: 100 krad (Si)
- SEL Immune to a LET of 109 MeV-cm2/mg
- SEU Immune to a LET of 109 MeV-cm2/mg
Packaging options (1.27mm pitch, 17mm sq. body):
- 168-CLGA
- 168-CBGA
- 168-CCGA
Standard Microcircuit Drawing 5962-08243 - QML Q and Q+ 

- High altitude avionics
- X-ray Cargo Scanners
- Test and Measurement
- Networking, telecommunications and mass storage

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